High-Bandwidth Memory Interface by Chulwoo Kim Junyoung Song & Hyun-Woo Lee

Author:Chulwoo Kim, Junyoung Song & Hyun-Woo Lee
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

Fig. 3.15Delay line mismatch effect

3.5 CAS Latency Controller

Data is output from DRAM after a predefined number of cycles. These cycles are programmed by an MRS (Mode Register Set) command. This is called Column Address Strobe (CAS) Latency and is defined as the synchronous interval time between the READ command from the MCU and the DQs from the DRAM. In order to issue a READ command with a column address to DRAM, an active command should be issued first with row address. There should be an interval time between a RAS (Row Address Strobe) command and CAS command with the same back. During the initialization sequence, the CL is programmed by an MRS command and the DLL reset command issued. DRAM counts the internal clock cycle to calculate data output timing programmed as CL. One of the output enable control schemes is depicted in Fig. 3.16. The output-enabling time is easily calculated by a simple shift register. However, because the operating frequency goes up and the negative delay is generated by the DLL, it is hard to calculate the output-enabling time through simple shift register. Therefore, output enabling circuits should perceive the time of internal clock delay and negative delay of the DLL. Figure 3.18 shows the countered CAS latency control block (CCLC) proposed in another study [9]. The CCLC has an adder, a counter, an OE SHIFT REGISTER, a DELAY MODEL, and an RCDL (register controlled delay line), which is the same as the one in the DLL. The DLL makes a DLL_CLOCK according to the delay model. Eq. (3.9) is defined after locking:

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